Postdoctoral Researcher System Technology Co-Optimization Of Vertical FET For 3D Partitioned SOCs

As our Post Doc researcher System Technology Co-optimization of Vertical FET for 3D partitioned SoCs you will have the opportunity to work on our cutting-edge 3D technology and innovate the SoCs architecture, which results in an increasing computing power and lower energy consumption.


What you will do

The CMOS scaling driven by Moore’s law is facing several challenges arising from the increasing complexities and abilities of photolithography to pattern the required feature sizes. It revealed that the two-year timeframe of Moore’s law has been dropped and moved to a three-year cadence (tick-tock-tock) of optimizing technology and micro-architecture for the first time in sub-14nm technology nodes.

A large number of disruptive and immerging technologies including vertical gate-all-around (GAA) and complementary MOSFET (CFET) have been investigated to maintain a continual scaling of CMOS technologies. In parallel to them, the heterogeneous integration of multiple technologies on the same logic die, which are becoming more viable with the advances in 3D wafer-stacking and sequential 3D technologies, can open a new landscape for EDA tools and design methodologies.

You will be involved in circuit design and system optimization for 3D integration where devices are expected to feature vertical channels and/or vertically stacked device. Based on System-Technology Co-Optimization (STCO) framework you will interact with our top edge process engineering teams to develop different fundamental circuit blocks such as SRAM in vertical/stacked FET CMOS technology. You will also optimize these circuit blocks for 3D partitioned System-on-Chips (SoCs) to ensure a smooth power-performance-area and cost evaluation flow that assess the technology from process capabilities up to digital system requirements.

You would also closely interact with imec’s top class customers to provide them with early solutions to their design requirements and understanding of process-design interactions.


Your responsibilities will include:

  • Circuit design and optimization using vertical FET for 3D partitioned SoCs
  • Close interaction with process and system benchmarking teams in a STCO platform that includes lithography, device modeling, process integration, and system PPA


What we do for you

  • We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
  • We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through, ‘our corporate university’, we actively invest in your development to further your technical and personal growth.
  • We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary.

Please click here to apply:

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